Applications are invited from the interested candidates for the post of JRF to work on the R&D project
titled “Sophisticated Optimised DC-DC Converter for Charging Electric Vehicle Using Reliable GaN
devices and Planar Magnetics” supported by Science and Engineering Research Board (SERB), New
Delhi. The selected candidate will be appointed initially for one year (on contract) and the services will
be extended for next two years based on the performance review.
Post name Junior Research Fellow
Area specialization Power Electronics
Maximum duration 3 Years
Salary Rs. 31,000/- + 16% HRA
(Per month for two years)
Rs. 35,000/- + 16% HRA
(Per month for third year)
No of position One (01)
Educational Qualification:
B.E./B.Tech in Electrical & Electronics Engineering and M.Tech./MS(R)/M.E./equivalent in
Electrical & Electronics Engineering with expertise in Power Electronics. Candidates must have
at least 6.5/10 CGPA or 60 percent marks in aggregate from a recognized Technical Institute or
University as a Full-Time program. Those who are appearing for M.Tech/M.E. last semester may
also apply. Proof of M.Tech/M.E. certificate has to be provided during the time of interview.
Desirable: GATEqualified,Expertise in MATLAB, PSCAD simulations, experience in development
ofpower electronics hardware, experience in FPGA, DSP coding and project management.
Age limit: 35 years
Interested candidates must apply with the following documents:
(1) JRF Application form
(2) CV
with passport-sized photograph,
(3) Scanned copies of educational certificates and mark sheets
from class XII onwards
(4) GATE qualified certificate and
(5) Scanned copies of Proof for research
experience, special achievements and publications, if any. The soft copies of all the above
documents as single pdf with file name as “YOUR_NAME_JRF.pdf” must be emailed to the
Principal Investigator (Dr. R Kalpana) on or before 11th September 2023 with subject
“Application for JRF” and hard copies of all the documents should be send to the address
for correspondence given below on or before 15
th September 2023. The email address for
correspondence is given below. No TA/DA will be paid for attending the written test/interview.
The appointment will be on a purely temporary basis co-terminus with the project. Candidates
who are already employed should produce relieving certificate from their employers, if selected.
The shortlisted candidates with the date of written test/interview will be intimated by email
only.
Address for Correspondence:
To
Dr. R. Kalpana
Principal Investigator and Assistant Professor,
Dept. of Electrical & Electronics Engineering,
NITK Surathkal, Mangalore,
Karnataka, India -575025